USPTO Patents Application 10071373

Abstract of the Disclosure

A multiply-accumulate circuit includes a compressor tree to generate a
product with a binary exponent and a mantissa in carry-save format. The product is
5 converted into a number having a three bit exponent and a fifty-seven bit mantissa in
carry-save format for accumulation. An adder circuit accumulates the converted
products in carry-save format. The adder operates on floating point number
representations having exponents with a least significant bit weight of thirty-two, and
exponent comparisons within the adder exponent path are limited in size. The adder
10 circuit includes intermediate registers to provide multi-threaded capability. Products
interleaved in time are accumulated into separate sums simultaneously.

Attorney Docket 884.584US1

26

Client Ref.No.P12603